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DS1722
inactive clock is determined by sampling SCLK when CE becomes active. Therefore, either SCLK
polarity can be accommodated. Input data (SDI) is latched on the internal strobe edge and output data
(SDO) is shifted out on the shift edge (See Table 6 and Figure 3). There is one clock for each bit
transferred. Address and data bits are transferred in groups of eight, MSB first.
 
FUNCTION TABLE Table 6
MODE
CE
SCLK
SDI
SDO
Disable Reset
L
Input Disabled
Input Disabled
High Z
Write
H
CPOL=1*
Data Bit Latch
High Z
 
7 of 14
 
CPOL=0
Read
H
CPOL=1
 
CPOL=0
X
Next data bit
shift**
*CPOL is the Clock Polarity bit that is set in the control register of the microcontroller.
** SDO remains at High Z until eight bits of data are ready to be shifted out during a read.
 
NOTE: 
CPHA bit polarity must be set to 1.
 
SERIAL CLOCK AS A FUNCTION OF MICROCONTROLLER CLOCK
POLARITY (CPOL) Figure 3 
 
 
CPOL=1
 
 
 
 
 
CPOL=0
CE
SCLK
CE
SCLK
INTERNAL
STROBE
SHIFT
INTERNAL
STROBE
SHIFT
 
 
 
 
NOTE: 
CPOL is a bit that is set in the microcontrollers Control Register.
 
ADDRESS AND DATA BYTES
Address and data bytes are shifted MSB first into the serial data input (SDI) and out of the serial data
output (SDO). Any transfer requires the address of the byte to specify a write or a read, followed by one
or more bytes of data. Data is transferred out of the SDO for a read operation and into the SDI for a write
operation.
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